The present disclosure relates generally to memory allocation, and more particularly, to minimizing Translation Lookaside Buffer (TLB) faults.
TLB is a cache that is used by memory management hardware to improve the speed of virtual address translation. Virtual address space in virtual memory is associated with an address range that is typically much larger than that of physical memory. The virtual memory address range starts at a base address and ends at an upper boundary address. This virtual memory address range is divided into pages, which may correspond during the execution of an application to various physical addresses. A virtual page number is mapped to a physical page number using the TLB. A lookup in a TLB table is performed to translate a virtual address to a physical address. If a valid TLB entry is found then its content is used to produce a physical address. If no TLB entry is found or the entry is not valid then a TLB fault (exception) is generated.
During normal operation in conventional systems, many processes are created and destroyed dynamically. This results in physical memory remap and reassignment each time the new process is created or requires additional dynamic memory. The process memory is built from available system memory pages which are not necessarily sequential. As a result, conventional systems may comprise many virtual pages, each requiring a slot in the TLB table in order to be translated into physical memory. Since the TLB size is typically limited (e.g., 64 entries), all of the pages cannot fit into the TLB. Thus, every time address translation is requested and the page is not found in the TLB, a TLB exception is generated. Handling of TLB exceptions may be very costly.